Accurate Timing and Power Characterization of Static Single-Track Full-Buffers

Index Sr. No. Title Page No. 1 Abstract 3 2 Introduction 3 3 Background 1. Static Single-Track Full-Buffer 2. Characterizing Delay and Power 4 5 4 Modeling SSTFB 5 5 Asynchronous ASIC Design Flow 6 6 Characterization Flow 1. Input Slew and Load Capacitance 2. Abstract For main stream acceptance of asynchronous circuits, a mature EDA tool flow is necessary that leverages off commercially available tools for synchronous circuits. A characterization methodology that supports back-annotated power and timing for high-performance asynchronous circuits based on the static single-track full-buffer template is presented here. The model takes into account the effects of input slew rate and output loading and is represented in a commercial library format. Experimental results show that back-annotated post P&R simulations using this library lead to less than 7.1 % error compared to detailed spice-level simulations that require orders of magnitude longer run-times.